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XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
1.3
Device Reset
The RESET (RESET#) input resets the internal registers and the serial interface outputs to their default state
(see Table 19 ). An active high (RESET) or active low (RESET#) pulse of longer than 40 ns duration will be
required to activate the reset function in the device. Following a power-on reset or an external reset, the M890
is software compatible with previous generation of UARTs.
1.4
5-Volt Tolerant Inputs
The M890 can accept and withstand 5V signals on the inputs without any damage. But note that if the supply
voltage for the M890 is at the lower end of the supply voltage range (ie. 1.8V), its V OH may not be high enough
to meet the requirements of the V IH of a CPU or a serial transceiver that is operating at 5V. Caution: XTAL1 is
not 5 volt tolerant.
1.5
Internal Registers
The M890 has a set of 16550 compatible registers for controlling, monitoring and data loading and unloading.
These registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER),
a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status and control
registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM/DLD), and a user accessible
scratchpad register (SPR).
Beyond the general 16C550 features and capabilities, the M890 offers enhanced feature registers (EFR, Xon1/
Xoff 1, Xon2/Xoff 2, DLD, FCTR, EMSR, FC and TRIG, SFR, SHR, GPIOINT, GPIO3T, GPIOINV, GPIOSEL)
that provide automatic RTS and CTS hardware flow control, automatic Xon/Xoff software flow control, 9-bit
(Multidrop) mode, auto RS-485 half duplex control, different baud rate for TX and RX and fractional baud rate
generator. All the register functions are discussed in full detail later in “Section 2.0, UART Internal Registers”
on page 27 .
1.6
INT Ouput
The interrupt outputs change according to the operating mode and enhanced features setup. Table 1 and 2
summarize the operating behavior for the transmitter and receiver. Also see Figure 26 through 29 .
T ABLE 1: I NTERRUPT P IN O PERATION FOR T RANSMITTER
FCR B IT -0 = 0 (FIFO
D ISABLED )
FCR B IT -0 = 1 (FIFO E NABLED )
INT Pin
(Intel or VLIO Mode)
IRQ# Pin
(Motorola Mode)
LOW = One byte in THR
HIGH = THR empty
HIGH = One byte in THR
LOW = THR empty
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or FIFO empty
HIGH = FIFO above trigger level
LOW = FIFO below trigger level or FIFO empty
T ABLE 2: I NTERRUPT P IN O PERATION FOR R ECEIVER
FCR B IT -0 = 0 (FIFO
D ISABLED )
FCR B IT -0 = 1 (FIFO E NABLED )
INT Pin
(Intel or VLIO Mode)
IRQ# Pin
(Motorola Mode)
HIGH = One byte in RHR
LOW = RHR empty
HIGH = One byte in THR
LOW = RHR empty
LOW = FIFO below trigger level
HIGH = FIFO above trigger level or RX Data Timeout
HIGH = FIFO above trigger level
LOW = FIFO above trigger level or RX Data Timeout
13
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